Dec 8 2009
K-micro (Kawasaki Microelectronics America), a leader in advanced ASICs, and Anritsu announced the development of the first test tool and methodology to analyze 10Gbps Ethernet Passive Optical Network (EPON) chips. The successful test of K-micro's CTXL1 10G EPON SerDes chip using Anritsu's Signal Quality Analyzer, MP1800A, paves the way for 10G EPON systems to be shipped.
Precise measurements of K-micro's CTXL1 10G EPON SerDes chip demonstrate its innovative burst mode lock time of '20nsec'. "We have worked with Anritsu, a company well-respected for its technology test solutions, to develop testing for EPON chips because our customers are ready to implement EPON applications and need to know that the chips meet the specifications for the products," said Vijay Pathak, CTO at K-micro.
There are two major challenges to evaluate 10G EPON Optical Line Termination (OLT) burst mode SerDes:
- A Bit Error Rate Test (BERT) must examine only the delimiter and the payload, and calculate bit error rate. The sync pattern shouldn't be taken into account.
SerDes must keep the same latency for every burst. Or, BERT must have the capability to allow latency difference between bursts.
MP1800A's powerful Pulse Pattern Generator (PPG) and Error Detector (ED) easily and accurately calculate the bit error rate, and CTXL1's unique Built In Self Test (BIST) function can successfully align the latency on every burst so BERT is not required to compensate for the variation of the latency between bursts. These two cutting edge technologies met and made it possible to measure burst mode lock time at 10.3125Gbps with BER of better than 1.0E-12.
"Successfully testing K-micro's 10G EPON chip is an important step for the EPON applications market," said Wade Hulon, Vice President and General Manager, Americas Region at Anritsu. "The two companies worked side-by-side to overcome the challenges of testing this type of technology so that it could be made available to customers."
Source: http://www.k-micro.us/