Feb 23 2010
Current optical lithography techniques for patterning semiconductor devices are rapidly reaching their limits. While immersion lithography with double patterning appears to be extendible to 19nm for flash memory devices and potentially to 15nm logic designs, EUV lithography is viewed as the most likely successor.
However, it’s vital that EUV lithography and its related processes are production ready for this major transition – able to reach acceptable levels of productivity and yield. On February 24, Applied Materials will host an in-depth seminar to explore the techniques that will be required for cost-effective advanced scaling.
Titled “High-Productivity Technologies for Next Generation Lithography,” the forum will feature experts drawn from logic and foundry manufacturers, research consortia and the equipment sector. During a full day of technical presentations at the Sainte Claire Hotel in San Jose, California, the speakers will present the latest advancements in mask and wafer patterning, inspection and metrology that are enhancing both process precision and productivity.
Speakers: Chas Archie – Senior Physicist, IBM
Ben Bunday – Senior Member of Technical Staff, SEMATECH
Jo Finders – Fellow, ASML
Ted Liang – Senior Staff Engineer, Intel
Hans Stork – Chief Technology Officer of Silicon Systems Group, Applied Materials
Obert Wood – Principal Member of Technical Staff, GLOBALFOUNDRIES
Where: Sainte Claire Hotel,
302 S Market Street, San Jose, CA 95113
When: Wednesday, February 24, 2010
Schedule: 9:00am-9:30am Registration
9:30am-4:30pm Seminar program