Data center traffic has grown at a compound annual rate close to 30%, and about 75% of that traffic never leaves the building. Artificial Intelligence (AI) training clusters concentrate this movement into dense flows between accelerators, and turn the network into a large line item in every build. Switch silicon has absorbed much of that demand.
Image Credit: yucelyilmaz/Shutterstock
Switch Application-Specific Integrated Circuit (ASIC) capacity climbed from 0.64 Tb/s in 2010 to 25.6 Tb/s in 2020 as process nodes shrank from 40 nm to 7 nm. However, as aggregate bandwidth exceeds 51.2 Tb/s, front-panel pluggable optics reach physical limits. Silicon photonics enters here as the manufacturing route that lets operators buy bandwidth without buying that many discrete modules.1
Why Copper Sets the Price Floor?
Electrical links degrade sharply at AI-era signaling rates. For example, copper insertion loss can reach 5 dB/mm at 50 GHz frequencies. Additionally, printed circuit board traces can lose more than 6 dB when lane rates exceed 200 GBPS, and conventional pluggable connections can incur over 20 dB of loss across their transitions and long board runs.2
Every dB of loss impacts the system twice. Equalization circuits and retiming chips consume power to recover the signal, and this power usage contributes to cooling load, which ultimately translates into capital expenses for the facility. In contrast, optical fiber transmission at the board level reduces energy consumption by a factor of 100 compared to electrical board traces.2
Moving the Optics into the Package
Co-packaged optics places the photonic engine beside the switch ASIC and shortens the electrical path to millimeters. Pluggable modules consume 15-20 pJ/bit, while co-packaged systems operate at 5-10 pJ/bit, a reduction of more than 50%, which Broadcom pairs with a 40% lower cost per bit.3
The savings associated with co-packaged optics scale with switch capacity. A 51.2 Tb/s co-packaged switch has demonstrated 0.9 pJ/bit while doubling bandwidth against plug-and-play designs, and a 25.6 Tb/s system reduced full-traffic power by 25% compared with pluggable architectures. Larger switches therefore recover the added packaging investment faster than small ones.2
Shorter reach also simplifies the electronics involved. An extra-short-reach Serializer/Deserializer (SerDes) running at 112 Gb/s in a 7 nm Fin Field-Effect Transistor (FinFET) has reached 1.7 pJ/bit because the low-loss channel requires only light equalization. Stripping out complex digital signal processing reduces silicon area, recurring energy costs, and the number of components that can fail.1
Cost reduction depends on the fabrication base. Silicon photonic circuits are built on the mature processing infrastructure of silicon microelectronics, which allows the same chips to scale into large-volume production for optical transceivers, the highest-volume photonic product in the data center. Wafer economics therefore govern the final price an operator pays.4
The maturity of this technology is reflected in the quality of devices. Foundry-manufactured chips using shifted-polysilicon overlay gratings achieve fiber-to-chip coupling losses under 1 dB, and grating couplers designed with resonant-cavity enhancement achieve a 1 dB optical bandwidth above 100 nm. High-speed silicon modulators now push individual lanes past 300 Gb/s.4
Packaging choices also carry comparable weight. Fan-out wafer-level packaging of electronic and photonic dies delivers interconnects with 0.05 dB loss up to 28 GHz and reduces optical engine packaging cost as compared to through-silicon-via approaches. Material costs stay low because the process avoids expensive silicon interposers.2
Translating Physics into Price Per Bit
Operators purchase capacity, so the critical metric is cost per unit of capacity. The pricing for 400G-DR4 optical engines is projected to decrease from below $1.20 per Gbps in 2021 to below $0.60 per Gbps by 2024. Moreover, a 50% reduction in system-level cost per capacity compared to pluggable modules is considered achievable.1
The cost reduction is primarily driven by increased integration density. Many-channel photonic circuits combine waveguides, modulators, detectors, multiplexers, and V-grooves for passively aligned fiber attachment on a single die, and that passive alignment holds fiber-to-chip loss within 1.5 dB. Every function absorbed into the chip is one fewer part to align, test, and warranty.1
3D Integration Lowers the Floor
Research links now sit far below commercial energy figures. A 28 nm Complementary Metal-Oxide-Semiconductor (CMOS) electronic chip has produced transmitter and receiver front ends that together consume 120 fJ per communicated bit, against 240 fJ per bit for the previous largest single-chip system.5
Density arrives with that efficiency. 80 transmitters and eighty receivers occupy 0.3 mm² of combined chip area, carry 800 Gb/s in each direction, and yield 5.3 Tb/s per square millimeter of bandwidth density. Modest 10 Gb/s channels maintain high receiver sensitivity, while the array provides aggregate throughput.5
The design highlights the areas where costs are often concealed. A 2,304-bond copper-tin array at 25 μm pitch contributes only 10 fF per bond. This means that a packaging step that previously increased parasitic capacitance and power consumption now helps to retain the energy advantages of the photonic devices. Additionally, the measured bond strength of 114.9 MPa is important for ensuring high yield in volume manufacturing.5
What Still Adds Cost?
Light sources remain a major expense. An external laser package for a 6.4 Tb/s engine draws about 18 W, with laser chips and thermoelectric coolers accounting for nearly 70% of that figure. A 102.4 Tb/s switch needs 16 such packages and 288 W of laser power.1
The heat generated further compounds the problem. Raising a micro-ring resonator from 20 °C to 28 °C shifts its spectrum by 0.4 nm and changes insertion loss by up to 9 dB, and a modeled switch chip ringed by 16 optical modules reached 151.76 °C under forced air. Liquid cooling lowered one electronic die by 35 °C in testing.1
The Economic Picture
Silicon photonics reduces the cost of AI data centers along four paths at once. Energy per bit falls, bandwidth per package rises, discrete component counts shrink, and CMOS foundry volumes spread fixed costs across more units. Each path compounds the others as switch capacity climbs toward the 102.4 Tb/s generation.3
The purchase price will determine the pace of adoption. A power reduction alone is insufficient to displace mature front-panel pluggable optics, so co-packaged systems must achieve a compelling price point supported by agreed-upon industry standards before they become the default choice for the largest AI training clusters.1
References and Further Reading
- Tan, M. et al. (2023). Co-packaged optics (CPO): Status, challenges, and solutions. Frontiers of Optoelectronics, 16(1), 1. DOI:10.1007/s12200-022-00055-y. https://link.springer.com/article/10.1007/s12200-022-00055-y
- Gao, H. et al. (2025). Heterogeneous Integration Technology Drives the Evolution of Co-Packaged Optics. Micromachines, 16(9). DOI:10.3390/mi16091037. https://www.mdpi.com/2072-666X/16/9/1037
- Tian, W. et al. (2024). Progress in Research on Co-Packaged Optics. Micromachines, 15(10). DOI:10.3390/mi15101211. https://www.mdpi.com/2072-666X/15/10/1211
- Zhou, X. et al. (2024). Silicon photonics for high-speed communications and photonic signal processing. Npj Nanophotonics, 1(1), 27. DOI:10.1038/s44310-024-00024-7. https://www.nature.com/articles/s44310-024-00024-7
- Daudlin, S. et al. (2025). Three-dimensional photonic integration for ultra-low-energy, high-bandwidth interchip data links. Nature Photonics, 19(5), 502-509. DOI:10.1038/s41566-025-01633-0. https://www.nature.com/articles/s41566-025-01633-0
Disclaimer: The views expressed here are those of the author expressed in their private capacity and do not necessarily represent the views of AZoM.com Limited T/A AZoNetwork the owner and operator of this website. This disclaimer forms part of the Terms and conditions of use of this website.