LiDAR (light detection and ranging) is the optical equivalent of radar. LiDAR, as an active sensor that acquires 3D information, plays critical roles in remote sensing, defense, and autonomous driving.
A LiDAR is made up of three major modules: transmitting, beam steering and receiving. It measures the distance between targets by illuminating them with laser signals of specific wavelengths, and it obtains additional 3D information by mechanically or electromagnetically scanning the target’s surface.
The ToF ranging principle, which modulates laser beams in the time domain, is a popular LiDAR distance measurement method. The emitter sends a laser pulse to a target, and the receiver acquires the reflected laser pulse. ToF measures range by counting the round-trip flight time of laser pulses emitted between the LiDAR and the target.
Timing is essential for ToF LiDAR distance measurement; its precision is critical to the LiDAR’s ranging precision. A TDC is used to measure the time interval between the emission and arrival of laser pulses to get the correct timing. TDC is a chip that counts the time between start and finish signals and reverts it to the measurable digital medium.
A time–analog and analog-to-digital converter can quantify time intervals down to the picosecond range and transform time intervals from analog signal to digital signal.
The two main implementation methods are ASIC-based TDC realization and FPGA-based TDC realization.
The goal of a recent paper was to illustrate a low-cost digitally integrated LiDAR with TDC that is completely FPGA-controlled and processed in a low-end FPGA chip with constrained configurable logic block resources.
Numerous MCU and ASIC chips are needed for a LiDAR system to realize the control and processing features of a 2D LiDAR, such as pulse control, motor control, ToF calculation, and data processing.
An FPGA, with its ability to perform parallel and simultaneous processing, can realize high-speed computation in the form of a low-cost coprocessor. The logic functions of a 2D LiDAR are integrated into a single low-end FPGA in this paper.
The ToF spanning principle is to quantify the travel time of particles or waves between the emitter and the target. Counting clock pulses is the most basic method for determining the time interval between two events.
The pulse counting method works based on calculating the number of system clock signals produced by the IHIT signal during its valid time. It is simple to implement in an FPGA by starting and finishing a counter.
Figure 1 depicts the delay line’s operating principle. The delay line is made up of several delay cells and a D-type flip-flop (FFD) array. These delay cells are connected in a series to form a tapped delay line. The start signal is infused from the delay line’s head and continues to perpetuate in a specific direction along the entire line. The state of the delay tap in binary adjustments each time the signal passes through a delay cell.
Figure 1. The architecture of the delay line. Image Credit: Huang, et al., 2022
The fast carry logic with the peek element is CARRY4, which is situated in the slice of the configurable logic block and can be used as the time interpolator to construct the tapped delay line. Figure 2a represents a simple schematic of CARRY4 in FPGA.
Each CARRY4 cell is made up of four multiplexers (MUXCY) and four XOR gates. Port CI is the start signal’s input, and port CO3 is the delay line’s output. A long delay line is formed by cascading several CARRY4 cells into an array. Figure 2b depicts the use of CARRY4 cells in delay line logic.
The time resolution of the FPGA-TDC is calculated by the time interval of the signal crossing a delay cell, which is similar to the time needed for signal propagation from Cl to CO3.
Figure 2. (a) CARRY4 elements in Xilinx FPGA; (b) delay line structure. Image Credit: Huang, et al., 2022
Figure 3 depicts the time measurement procedure. The start signal is at a high logical level in the beginning, and the coarse counter begins to work concurrently. The fine counter is stimulated when the stop signal is powered up.
Figure 3. Fine and coarse time measurements. Image Credit: Huang, et al., 2022
Results and Discussion
When the input signal is greater than the system clock, it is essential to narrow it while keeping the delay line engaged within one system clock. As a result, the delay line could acquire one available conversion value per input signal from a pool of possible input signals. Figure 4 depicts the input filter schematic and simulation results.
Figure 4. Input filter schematic and simulation result. Image Credit: Huang, et al., 2022
A ZYNQ-7010 (XC7Z010) SoC was used to implement the proposed FPGA-TDC. Figure 5a depicts the proposed TDC implementation block diagram.
Figure 5. (a) Block diagram of TDC and average LSB simulation; (b) TDC timing simulation. Image Credit: Huang, et al., 2022
Figure 5b depicts the FPGA-TDC simulation results, such as the start, stop, and IHIT signals, coarse time, and a fine time. The IHIT signal is fully defined by the rising edges of the start and stop signals.
The coarse counter acquires the measurement value when the stop signal arrives. The fine value was calculated when the next rising edge of the system clock arrives. By incorporating the coarse and fine counters, the exact time interval is derived.
The semiconductor fabrication procedure and external factors have an impact on the TDC’s LSB. The differential nonlinearity (DNL) function is used to analyze the LSB difference between both the converted and ideal values, and the integral nonlinearity (INL) is the DNL accumulation sum. DNL and INL are determined using a standard code density test method and bin-by-bin calibration.
The technique works on the principle of generating a large number of external random pulses as the TDC input and recording the times of each delay cell. The statistical code measurement is used to assess the overall resolution. Each time, the counting result is saved in the system’s random access memory (RAM). Figure 6 depicts the RAM setup process.
Figure 6. Code density statistics diagram. Image Credit: Huang, et al., 2022
After around 10,000 points were collected, the hit pulse injection was stopped, and a PC for data analysis perused the values of each address in RAM out. Figure 7a depicts the statistical data of each carry series.
The DNL and INL were evaluated over the full range of the delay line in the TDC after bin-by-bin calibration and acquired through the code density test. Figures 7b and c show the results: the DNL is within 1 LSB and the INL is within 2.5 LSB.
Furthermore, excessive resource utilization in an FPGA hurts the layout and wiring inside, causing the system to become more unstable. Figure 7d summarizes the source utilization in the FPGA after synthesis and implementation.
Table 1 shows the resource utilization in full configuration, where only 2112 DFFs, 1056 LUTs, and 8 IO ports are used. These results demonstrate that the proposed TDC uses few resources. Table 2 shows the energy consumption of the FPGA-TDC, which is very low.
Figure 7. (a) Statistical analysis of the TDC bins; (b) DNL; (c) INL; (d) FPGA resource utilization. Image Credit: Huang, et al., 2022
Table 1. The TDC resource utilization. Source: Huang, et al., 2022
Table 2. Power consumption. Source: Huang, et al., 2022
When contrasted to some initially published works using TDL techniques, the FPGA-TDC has a limited resource cost, as shown in Table 3.
Table 3. Comparison of resource utilization. Source: Huang, et al., 2022
||Utilization (LUTs, DFFs)
A pulsed laser diode (LD) is small in volume, with a high peak power and conversion rate. Figure 8 shows the driver circuit schematic—the laser diode is an Osram SPL PL90-3 at 905 nm wavelength from Munich, Germany. The LD requires a small trigger and energy storage to achieve high peak power.
Figure 8. Laser drive circuit. Image Credit: Huang, et al., 2022
Figure 9a depicts the circuit schematic. The DC-DC boost circuit shown in Figure 9b offers a high reverse voltage.
Figure 9. (a) Receiver circuit. (b) Bias voltage circuit. Image Credit: Huang, et al., 2022
Figure 10a depicts the transceiver module’s printed circuit board (PCB).
More precise measurements are possible with symmetrical transmitting and receiving lenses. This module incorporates the laser transmitting and receiving circuits, which are both fueled by the 5 V DC power supply. To cut power supply requirements, all components in the LiDAR prototype distribute a 5 V DC power supply.
Figure 10. (a) Laser transceiver module. (b) The prototype of the 2-D LiDAR system. Image Credit: Huang, et al., 2022
As shown in Figure 10b, the presented LiDAR system primarily consists of a motor, a reflector, an FPGA controller, and a laser transceiver module.
An infrared camera and an oscilloscope were used to test the laser spot size and pulse waveform. The laser spot, recorded by the infrared camera, is shown in Figure 11a, where it is collimated through a 38 mm lens. At a distance of 2 m, the laser spot has a diameter of about 3 cm.
The oscilloscope captures and visualizes the FPGA trigger signal (top) and the distributed pulse signal (bottom) in Figure 11b.
Figure 11. (a) Laser spot. (b) The waveforms of the trigger signal and transmitter pulse. Image Credit: Huang, et al., 2022
After many measurements, the LiDAR’s ranging data were adjusted and tested at 1.5 m and 3 m distances, as shown in Figure 12a. For each distance, 2000 points were evaluated, and almost all of them were very close to the true distance, demonstrating the timing and ranging precision.
Figure 12b depicts the deviation—most of the points are very close to the ground truth distance with very little deviation, indicating a distance measurement precision of around 0.02 m.
Figure 12. Ranging test. (a) Distance test of 1.5 m and 3 m; (b) Deviation test of 1.5 m and 3 m. Image Credit: Huang, et al., 2022
Following that, targets with complex profiles and wide-view scanning were evaluated to validate the 2-D LiDAR’s ranging and scanning effectiveness. The frequent improvements of the obstacle edge in the horizontal direction are good targets for assessing the LiDAR.
One scanning clearly distinguishes the horizontal profile of the object in Figure 13a. The edge distance between the box and the wall is distinct and divergent.
An object with constant shape changes in the horizontal profile was evaluated in Figure 13b. The target contour is detailed and has almost no distortion when contrasted with the image.
Furthermore, wide-view scanning was evaluated, and the result, as shown in Figure 13c, revives the distance profile of the surroundings in the image. Figures 13d and e show the scanning outcomes of a wall corner and an obstacle with a round shape. On the right side of Figure 13, the distance between each point is depicted.
Figure 13. Scanning results. (a) Continuous object scanning; (b) Discontinuous object scanning; (c) Wide-view scanning; (d) Rectangular object scanning; (e) Circular object scanning. Image Credit: Huang, et al., 2022
In conclusion, a digitally transformed 2D LiDAR system with a lightweight and resource-saving TDC based on a symmetrical tapped delay line is incorporated in a low-end FPGA. To measure distance, the LiDAR utilizes the ToF ranging technique. It is made up of a homemade transceiver and a mechanical scanning structure made from off-the-shelf components.
This structure eliminates the expense and dimensions of LiDAR, which is important in consuming applications. Furthermore, due to its low cost and high integration, the presented digitally integrated LiDAR could be used in smart cities for robotic navigation, real-time pedestrian counting, truck overload tracking, social distance recognition, and traffic surveillance applications.
Huang, J., Ran, S., Wei, W., Yu, Q. (2022) Digital Integration of LiDAR System Implemented in a Low-Cost FPGA. Symmetry, 14(6), p. 1256. Available Online: https://www.mdpi.com/2073-8994/14/6/1256/htm.
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