With numerous reports placing PIC market growth at a CAGR1 upwards of 20% until 2022 and beyond, advanced automation for assembly and testing are crucially needed to enable high-volume production at viable cost-per-part.
Photonics technology is undergoing a transition toward greater integration, with multiple functionality and components now being combined onto a single device or within a small hybrid assembly, which is also known as a photonic integrated circuit (PIC).
Development has been directed at meeting requirements in terms of power dissipation and bandwidth density because it has been catering to the increasing datacom and telecom demands (data centers for cloud services and internet communications, respectively). Moving data in and out efficiently has become of paramount concern, over and above absolute processing power. As a result, these sectors have been the driving force behind the advancement of PICs.
Photonics is broadly recognized as an essential enabling technology for a wide variety of industrial processes and applications and so the PIC has naturally ‘trickled over’. This provides greater breadth to the growing infrastructure that is needed to support PIC eco-systems. The technology infrastructure is now considered by many to be mature enough to be mainstreamed.
The Emerging PIC Applications
Apart from datacom and telecom PIC applications, there are a selection of other strong market opportunities that exploit similar IR wavelengths (therefore benefitting from the existing development maturity at those wavelengths). There are also a wide variety of applications that have traditionally sought to utilize miniaturization at wavelengths that are more visible.
Figure 1. LIDAR and other optical sensor applications for automotive are set to grow significantly. Image Credit: pixelfit/iStock.com
The increasingly sophisticated optical sensing devices designed for (progressively autonomous) automotive applications are an example of the former. An increasing number of optical sensing devices, including LiDAR2, are being integrated into diverse automotive transport systems. This is a sector that is expected to undergo significant upheaval3 over the next 15 to 20 years.
Other markets that are worth considering include: virtual and augmented reality applications that are particularly important when they impact consumer markets; biophotonics, OCT and other biomedical sensing devices for decentralized testing (point-of-care diagnostics enabled by optofluidic and/or BioMEM devices); making more ‘sense’ of the environment around us using a multitude of networked sensors, typically referred to as Internet of Things (IoT); and also RF photonics for quantum systems, terahertz technology, defense and aerospace, and others.
The integrated opto-electronic devices feeding into these applications will need to be manufactured, assembled, tested and suitably packaged at high volume if the market forecasts are correct.
Figure 2. Augmented/virtual reality applications exhibit the volume scales that justify PIC use
Gearing Up for High Volume
Traditionally, device production has been geared to volumes between hundreds and thousands of components for most of the application spaces for photonics. Microelectronics and photonics have been individually manufactured and integrated discretely and then assembled as a complete device before they are tested and finally packaged. However, for larger numbers of photonic devices, perhaps hundreds of thousands or millions, ‘discrete’ and ‘individual’ are no longer viable procedures.
For PIC approaches, the diverse active/passive functional elements still need to be combined (hybridized) onto a base platform. Instead of one single technology platform that delivers all of the functionality required, there are several different material systems that contribute diverse functional building blocks to the PIC eco-system. It is important to ensure that these are highly integration-capable and so lend themselves to a wafer-level approach to assembly and test. It is also helpful to push singulation as far down the production line as possible. This is similar to the case for CMOS – a pathway to high-volume and wafer-scale production is opened up by reducing element diversity by rationalizing them down to a reduced number of mutually compatible micro-platforms.
Figure 3. Discrete assembly and test approaches have been acceptable at low volumes, but are entirely unrealistic at much higher manufacturing volumes.
The move towards greater opto-electronic integration actually requires a convergence of photonics and electronics across all aspects of production – design, manufacturing, assembly, test and packaging – and not just in terms of component manufacturing. The main caveat to this idea is that the current (elementary) development status of the PIC eco-system infrastructure contrasts distinctly with the robust maturity, automation level and scale (i.e. number of wafers) that are common to CMOS processes for microelectronics production.
This convergence will not happen overnight due to the disparity between infrastructure maturity for PICs compared to CMOS, which amounts to approximately 4 decades. However, there may be opportunities to transfer the knowledge gained in CMOS directly over to PIC. For example, the cost of assembly, testing and packaging of conventional CMOS chips was reduced down to the order of 10-20% of the total cost of production by the in-line test procedures.
Optical Assembly and Testing Procedures as the Bottleneck
Conceptually, the overall production task for PICs is the same as for conventional microelectronics. The greater complexity is introduced by optical probing:
- The diversity of optical characteristics to be measured – spectral or polarization properties, multiple (fiber) channels, transmission losses and temperature sensitivity
- Either assembly or probing (testing) of optical waveguides or fiber elements requires sub-100 nm positioning, compared to the upwards of 80 x 80 µm pads for electrical contacting
- The optical connections employed must provide for high accuracy, consistency and reliability, with the associated process time contributing significantly to overall device cycle time
These unique requirements have two consequences and are at odds with the idea that CMOS knowledge can be directly transferred to PICs. The first of these is that the assembly processes for PICs last between a few tens of seconds to several tens of minutes and this places strict requirements on the complexity of the machinery that is designed to achieve these tasks. It is very difficult to achieve sufficiently short cycle time without jeopardizing yield, even for the discrete assembly of singulated PICs into devices.
Figure 4. Coupling a fiber array to a PIC using an alignment system with 6 degrees of freedom
The second problem is that, as PIC testing requires both electrical and optical probing, testing procedures gain an additional layer of complexity. Each method of probing carries its own set of parameter-specific requirements (DC/low frequency and RF for electrical) and needs very different positional accuracy).
In order to solve these problems, a typical hybrid optical/electrical probe head for PICs will commonly exhibit a layout that caters to the more demanding optical requirements first. ficonTEC has been pursuing this exact approach in certain initiatives and projects and it would be invaluable to have an opportunity to explore requirements in a real manufacturing setting.
The slightly out of date but generally accepted situation for PICs4 is that front-end procedures only contribute 20% to the overall production cost whilst back-end procedures (assembly, packaging and testing) contribute approximately 80%. Rationally, a combined suite of optical and electrical testing procedures must now be considered so it is unrealistic to expect congruity with CMOS in this aspect. However, it might be reasonably assumed that adopting the establish CMOS-style in-line test infrastructures and procedures, as far as is practical, could help to minimize back-end costs.
Assembly and Test for Higher Volumes
A transition to wafer-level-capable procedures is necessitated by increasing volumes. In the wafer environment, overall pin count, diverse optical test parameters and coupling type/accuracy/speed all present issues along the process chain. Furthermore, thermal considerations become more important for the many optical features present on a PIC that are temperature sensitive or generate heat.
Since reworking following an assembly step is nearly impossible in most applications, the specialized requirements of PIC device manufacture mean that testing is an increasingly integral part of the assembly cycle. However, by utilizing careful design in the development phase and detailing explicitly what needs to be tested, when and to what level of requirement, and by providing an appropriate probing approach, such issues can be alleviated.
With regards to coupling, edge coupling offers some practical advantages5, however, unless additional intermediate process steps are introduced, it is not usually accessible before dicing. Device access at wafer level is provided by grating couplers (VGCs), with one of the approaches incorporating VGCs as ‘test only’ temporary structures during manufacturing (removable optical test points)6. Another option is a combination of both – surface coupling for wafer-level testing even when edge coupling the packaged device.
It is also important to consider the characterization procedures that can occur at both the module level and as a post-process device qualification test. In-line characterization and final device testing might have different requirements. These procedures also need to account for the application-specific needs, for example hermiticity and/or environmental needs differ greatly between biomedical andTelcordia applications. Lastly, there may be additional third party tests that require incorporation.
Generally, the assembly layout and associated process requirements in PIC production are defined by the optical followed by electrical I/O requirements. If possible, electrical, optical, fixturing and layout issues should be considered as early as possible in order to minimize conflicts. Unfortunately however, rather than addressing aspects such as automated assembly and scalability, these considerations still mostly come from the immediate device-specific needs. In particular, high-volume products tend to lean toward specifically adapted solutions in order to achieve best performance, optimum size, and/or cost savings.
An ‘optical first’ approach may, experience suggests, prove more favorable. Practical concepts for pre-alignment of optical probing and a certain degree of parallelism for wafer-level testing combined with optical/electrical probe approaches are required. However, at the same time there is no way around the greater implementation of automation.
Projects and Initiatives
ficonTEC has been awarded an order by AIM Photonics7 for a new wafer-level tester complete with robotized wafer loading, in one of many parallel activities aimed at a higher level of photonics integration. With fully automated test cycles for both vertical grating and edge couplers, the system is designed to handle all optical and electrical testing procedures flexibly for wafer level and singulated chips.
Another route to small and medium-volume production of packaged PICs is provided by a collaboration with PIXAPP8. Solutions will be developed for four different application domains – fiber sensing, datacom and telecom and bio-sensing – each with its own array of specific challenges in terms of costs, expected reliability and packaging. The collaboration is coordinated by the Tyndall National Institute9, in Cork, Ireland. PIXAPP will provide industrial users with single-point access to a complete overview of the PIC supply chain and link design tools to automated test, assembly and packaging. ficonTEC hopes to develop a better understanding of PIC assembly and testing needs in different segments of the market by this long-term interaction with a diverse range of partners and their requirements.
Figure 5. Key focus areas for the PIXAPP photonics packaging pilot line (courtesy of PIXAPP)
Additionally, ficonTEC has worked with various high-profile global technology leaders on projects that already need wafer-level processes in production and has gained significant experience from this. The themes discussed above are mirrored in the highlights from a few of these projects:
- Innovative assembly development aimed at reducing cycle time for low-cost air purity sensor devices intended for very high-volume automotive applications
- Using a VGC to couple fiber onto a PIC in a medium-volume TOSA/ROSA application
- Developed custom handling systems for innovative surface connector technology that is designed to ease on-chip coupling (and testing)
- Undertaking significant process automation development in order to reduce process time for the assembly of silicon photonics components destined for datacom applications
ficonTEC always works very closely with the customer development teams to fully understand these requirements and either work with the customer to develop required systems or to tune these within the framework of the available system capabilities. In some instances, these collaborations are already implementing necessary system and process changes in order to upscale production.
This is not just as multiple production lines operating in parallel on the same tasks, but also have an added layer of control which is provided by a common revision control server. As well as system-wide updates, individual process updates can now be implemented remotely and automatically.
There will be no way to avoid adopting these advanced automation procedures whilst also moving to higher production numbers and simultaneously trying to balance device sophistication against cost of production.
Although there seem to be many hurdles to the quick assembly and testing of PICs, photonic device production can be improved through increased automation and process development. As was the case for microelectronics, standards that define the overall eco-system will emerge and this will ultimately lead to more efficient test and assembly systems.
ficonTEC’s activities in testing, assembly, and packaging for photonic devices continue to expand. Expertise that comprises of over 600 globally installed systems since 2001 (with 85 of these in 2017 and 50 in Q1 2018) has shown that these still, almost exclusively, come with very varying requirements. However, the common aspect in the development of all of these systems has been the timely design of the production process around those tools that are available.
References and Further Reading
- Examples of market researchers predicting substantial PIC market growth potential: https://bit.ly/2k8vJ2q, https://bit.ly/2k5OYK1, and https://bit.ly/2wRMzvX
- LiDAR Technology: https://bit.ly/2IWZTVp
- Automotive sector volatility and growth potential: https://bit.ly/2s1zjiC
- PIC roadmap example: JEPPIX Roadmap 2018, p.37
- ‘Wafer-scale high-density edge coupling for high throughput testing of silicon photonics’, R. Polster, et al, OFC 2018 – see also AIM Photonics
- ‘Towards autonomous testing of photonic integrated circuits’, M. Milosevic, Proc. SPIE 10108, Silicon Photonics XII, 1010817 (2017/02/20)
- Link to Aim Photonics: http://www.aimphotonics.com/
- Link to PIXAPP: https://pixapp.eu/
- Link to Tyndall National Institute: https://www.tyndall.ie/about-us
- Link to Euratom EU Horizon 2020 program information: https://ec.europa.eu/programmes/horizon2020/en/h2020-section/euratom
- Link to EMVA program information: http://www.emva.org/
This information has been sourced, reviewed and adapted from materials provided by ficonTEC Service GmbH.
For more information on this source, please visit ficonTEC Service GmbH.