Wafer-Scale X-ray CMOS Imagers with 14-Bit Column Parallel ADC Concept

Table of Contents

Basic ADC Operation
Binning Implementation
Adaptations to Various Column Widths
CDS vs. DDS Readout
DFT Implementation
Performance Summary
Conclusion

Basic ADC Operation

The operating principle of the applied ADC is centered on a multi-slope thermometer code search methodology. This architecture was preferred to cyclic implementations or single-slope, successive approximation due to speed, size, and power consumption.

Basic 14-bit ADC architecture.

Figure 1. Basic 14-bit ADC architecture.

Figure 1 shows the related block diagram that consists of the following blocks: a bank of poly-poly capacitors and switches, a reference part with a multi-tap resistor ladder, a sample and hold circuit, an offset-compensated low-noise comparator, registers and counters to momentarily store the output data. Figure 2 shows the first step which is the pixel readout and related timing.

DDS pixel readout timing.

Figure 2. DDS (Double Delta Sampling) pixel readout timing.

The charge integration phase begins following pixel reset, and the output of the pixel (VPIXEL) gradually decreases due to photon-induced electrons. Towards the end of the integration phase, the column select (Sel) is activated, and VPIXEL is sampled and stored under control of the SHS timing signal on capacitors C1 and C2. In order to compensate for comparator offset, the input offset is stored on C2 at the same time. Soon after readout of the signal, the pixel is again reset and as a result of this, this value is sampled under control of the SHR timing signal. As the signal level of the pixel and comparator offset are already stored on C2, the result of the second sampling action is the subtraction of the pixel signal level and offset from the reset level. The column is deselected to finish the pixel sampling.

For the A-to-D conversion process, the reference part produces 4 ramps with accurate reference levels during 4 subsequent scans. From one ramp to another, the step size is decreasing as shown in Figure 3.

ADC conversion process.

Figure 3. ADC conversion process.

For this purpose, the reference part includes a bank containing 16 x 16 unit poly-poly capacitors and a resistor divider with 16 + 3 taps. Subsequently, the 4 different ramps are produced using the following combinations:

  • Ramp 1: groups of 16 unit capacitors with Vref
  • Ramp 2: one group of unit capacitors with one of the 16 taps of the divider giving Vref/16 steps
  • Ramp 3: unit capacitor and again one of the 16 taps of the divider
  • Ramp 4: unit capacitor and the three additional taps between reference ground and the first of the 16 taps giving steps of Vref/64

During the first scan, the first 4 most significant bits are determined and hence the sampled pixel level is compared with the ramp by using the low-noise comparator. If the ramp surpasses the stored pixel level, the reference output is reduced by a value equal to the last step. The next scan with smaller steps is then carried out to derive the next 4 bits. The conversion is said to be finalized when one scan (the last) for the 2 least significant bits and when three scans for 4 bits have been completed. The entire 14-bit conversion lasts 5.2 μs. Each step corresponds to a count associated with the bits weight of the respective scan. The 4+4+4+2 output bits of one ADC are integrated for all the columns in a serial fashion; line and frame sync pulses are added and brought off-chip by using an LVDS serial interface.

Binning Implementation

By averaging the pixel output of two adjacent rows, vertical binning is implemented. In order to increase the frame rate, the conversion process for two rows has to be conducted at the same time and therefore, the ADC requires a dual instead of a single input. This dual input can be realized by extending the sample and hold part of the basic single input ADC, as depicted in Figure 4.

ADC extensions to enable row binning.

Figure 4. ADC extensions to enable row binning.

The ‘No_binning’ switch is closed for normal operation. Consequently, the capacitor C1_odd is connected in parallel to C1_even and likewise C2_odd and C2_even. Alternately, the ‘Sel_odd’ and ‘Sel_even’ switches are closed in order to sample the pixel levels of the odd and the even rows, respectively. The ‘No_binning’ switch is opened for binning operation, and both select switches are closed simultaneously. The overall result is the intended averaging of both pixel levels. As shown in Figure 5, readout of the pixel array is implemented; one input of a dual input ADC is connected to the odd rows and the other to the even rows.

Row and column arrangement in case of binning.

Figure 5. Row and column arrangement in case of binning.

The rows are readout in pairs under control of the V- (row) driver situated in the middle column of the pixel array. Both select signals control the ADC input switches and also the switches to concurrently connect the pixel output of two rows to their respective column busses.

If sensor tiles are vertically butted with a butting distance of a single pixel pitch, geometrical image distortion might take place if pair-wise readout for both sensor tiles is done in an identical way. For example, if the gap is ignored, distortion caused by vertical compression occurs and if the gap is treated as a row pair, the single pitched gap is extended to a double pitch distance in the resulting image. This issue is solved by implementing a single row shift and activation hereof for one of both sensors. Figure 6 shows the principle.

Row pairs in case of shifted binning.

Figure 6. Row pairs in case of shifted binning.

For one of the sensor tiles (either the top or the bottom one), the row pairs are moved one row in a vertical direction, which leads to a single top and bottom row. For both of these, only a single select line is activated and one ADC input is used, and therefore the pixel output is not averaged. For the top row, this means the output of one row is considered for the combination of an active row, and the (non-active) gap and distortion, caused by geometrical expansion or compression, is avoided.

Adaptations to Various Column Widths

The width of a single column ADC measures about 67 µm. If the pixel pitch is, for example, 134 µm as shown in Table 1, two ADCs fit in a single pixel pitch. Subsequently, the two ADCs are both separately connected to a row, and conversion of both rows is carried out in parallel. In this fashion, the frame rate can be increased to a large extent.

Pixel pitches of 50, 100, and 200 µm are accommodated by the ADC width as follows: for the smallest pixel, the width of the ADC is extended to 100 µm, followed by applying a dual input to serve two pixel columns. For pixel pitches measuring 100 µm, a dual input ADC is employed to read out two vertically adjacent rows. For pitches measuring 200 µm (and 134 µm), two ADCs are available for one column to increase the frame rate.

CDS vs. DDS Readout

An alternative to the above-described DDS pixel readout method, CDS offers a solution to lower the pixel reset noise. Using a floating diffusion, on-chip CDS is applied to pixel architectures. Figure 7 shows the readout timing with pixel reset prior to signal sampling. Compared to DDS readout, the reset value sampling and order of signal are reversed. With decreasing pixel output signal level, the input of the comparator also decreases. For this readout technique, the basic ADC implementation is adapted through a simple reversal of the top and bottom connections of the resistor ladder in the reference part. Rather than a rising edge, the generated ramp lies in the opposite direction (falling edge) corresponding to a decreasing signal level at the input of the comparator.

CDS pixel readout timing.

Figure 7. CDS (Correlated Double Sampling) pixel readout timing.

External CDS for pixels without a floating diffusion is also possible. To accomplish this, an artificial reset reference VART is used rather than the pixel reset value. Figure 8 shows this (external) reference source VART and its connections.

Adaption for external CDS (DDS readout timing scheme).

Figure 8. Adaption for external CDS (DDS readout timing scheme).

Two conversions have to occur for one net pixel output value; the first is the pixel reset value minus this reference voltage VART and the second is the pixel signal level minus the same reference voltage. The first result is momentarily stored externally and then the second result is digitally subtracted from the first.

DFT Implementation

For test and validation purposes, digital and analog DFT (Design For Test) circuits are implemented. These circuits are:

  • Buffers for probing internal ADC nodes
  • Artificial pixel
  • Programmable generator for numerous digital test patterns to validate the LVDS interface

Figure 9 shows the principle of the artificial pixel. For standard operation, the pixel array’s photodiodes are readout by connecting them to the column bus through the row select switches. Disconnecting all the photodiodes and closing the artificial pixel switch can activate the artificial pixel. Following this, an external voltage can be applied to the column bus. Just like the photodiode output, an N-most source follower is used as a buffer in the same manner. The artificial reset reference is used as reset level that is identical to external CDS operation. It is possible to probe the critical ADC nodes by closing the related switch and viewing the buffered voltage available on the dedicated sensor pad ‘Analog Test Out’. Instances of such critical nodes are: the column bus voltage (both to check settling behavior), the pixel reset voltage, and the generated voltage ramp.

Analog DFT implementation.

Figure 9. Analog DFT implementation.

Performance Summary

Table 1 sums up the performance of a typical imager with the ADC implementation described in this article and 134 µm pixel pitch.

Table 1. Performance summary of one out of the range of X-ray detectors.

. .
Technology 0.35 μm 2P4M CMOS
Device Dimensions 104 x 142 mm2
Pixel Pitch 134 μm x 134 μm
Resolution 768 (H) x 1024 (V)
Full Well Capacity 155 ke- / 567 ke-
Conversion Gain 13 μV/e- / 3.5 μV/e-
Noise Data Double Sampling 67 e- / 148 e-
Dynamic Range
   - DDS mode
   - External CDS

67.3 dB / 71.7 dB
77.5 dB
Quantum Efficiency > 50% @ 500 nm
Dark Current @ 60 °C 60 ke- / pix.sec
AD Conversion Depth 14-bit
Max. Data Rate per LVDS output 560 Mbps
Frame Rate 100 fps
Sensor Power Consumption 1.2 W
ADC Clock Frequency 10 MHz
#Clock cycles for one conversion 52
Supply Voltages 3.5 V (Analog + Digital)
ADC Current Consumption 90 μA (3.5 V)
LVDS buffer supply 2.7 V
ADC Reference Voltage 2.8 V

 

A sensor tile and a fully assembled detector are shown in Figures 10 and 11, respectively while Figure 12 shows an X-ray image of a clinical phantom captured with one of the detectors beyond the presented range.

wafer scale X-ray imager

Figure 10. Photograph of a wafer scale X-ray imager (100 µm pixel pitch variant) with the 14-bit column-parallel ADC including tile PCB.

complete X-ray detector

Figure 11. Photograph of a complete X-ray detector comprising a wafer-scale imager with the 14-bit ADC, scintillator layer for X-ray to visible light conversion and interfacing electronics.

Image captured with the wafer-scale X-ray detector.

Figure 12. Image captured with the wafer-scale X-ray detector.

Conclusion

This article has presented a 14-bit column-parallel ADC for wafer-scale X-ray CMOS imagers. The highly flexible concept and minor circuit extensions to the basic implementation are enough to serve a broad product range of detectors and multiple applications.

References

1. L. Korthout et al., “A wafer-scale CMOS APS imager for medical X-ray applications”

2. R.Reshef, et al., “Large-Format Medical X-ray CMOS Image Sensor for High Resolution High Frame Rate Applications”, International Image Sensor Workshop, June 2009

3. Steven Huang, et all.,”Design of a PTC inspired Segmented ADC for High Speed Column Parallel CMOS Image Sensor”.

4. S. Matsuo, T. Bales, M.Shoda, S.Osawa, B. Almond, Y. Mo, J. Gleason, T. Chow, I. Takayanagi,“ A Very Low Column FPN and Row Temporal Noise 8.9 M-Pixel, 60 fps CMOS Image Sensor with 14bit Column Parallel SA- ADC,” Dig. Tech. Papers, Symp. VLSI Circuits, pp.138-139, 2008.

5. M. Furuta, Y. Nishikawa, T. Inoue, S. Kawahito, “A high-speed, high-sensitivity digital CMOS image sensor with a global shutter and 12-bit column-parallel cyclic A/D converter,” IEEE J. Solid-State Circuits, vol.42, no.4, pp.766- 774, 2007.

Teledyne DALSA.

This information has been sourced, reviewed and adapted from materials provided by Teledyne DALSA.

For more information on this source, please visit Teledyne DALSA.

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